1. Field of the Invention
The present invention relates to an ESD protection structure and, more particularly, to an ESD protection structure that protects against power-on and power-off ESD events.
2. Description of the Related Art
An integrated circuit chip can be destroyed when an unintentional voltage spike, known as an electrostatic discharge (ESD) event, is applied across the pins of the chip. Thus, to guard against unintentional voltage spikes, current-generation chips include ESD protection circuits that protect the chips from ESD events.
FIGS. 1A-1B show schematic diagrams that illustrate a prior-art ESD protected chip 100. As shown in FIGS. 1A-1B, chip 100 has a number of I/O cells 110, including I/O cell 110-1 and I/O cell 110-2, and an ESD protection circuit 112 that is connected to each of the I/O cells 110. The I/O cells 110, in turn, have a number of pins 114, including a pin 114-1 and a pin 114-2, which provide external connections to the electrical circuits within the chip. In the present example, I/O cell 110-1 has a pin 114-1, while I/O cell 110-2 has a pin 114-2.
As further shown in FIGS. 1A-1B, ESD protection circuit 112 includes a number of upper diodes 116, including upper diodes 116-1 and 116-2, that are associated with the I/O cells 110 so that each upper diode 116 is connected to a pin 114. For example, upper diode 116-1 is connected to pin 114-1 and upper diode 116-2 is connected to pin 114-2. ESD protection circuit 114 also includes a number of lower diodes 118, including lower diodes 118-1 and 118-2, that are associated with the I/O cells 110 so that each lower diode 118 is connected to a pin 114. For example, lower diode 118-1 is connected to pin 114-1 and lower diode 118-2 is connected to pin 114-2.
In addition, ESD protection circuit 112 includes an esdPlus rail 120, an esdMinus rail 122, and an ESD switch 124 that is connected between esdPlus rail 120 and esdMinus rail 122. EsdPlus rail 120 is connected to the cathodes of the upper ESD diodes 116 that are connected to the pins 114. Similarly, esdMinus rail 122 is connected to the anodes of the lower ESD diodes 118 that are connected to the pins 114.
Since the esdPlus and esdMinus rails 120 and 122 pass through each of the I/O cells 110, and are connected to each of the pins 114 by way of the diodes 116 and 118, rails 120 and 122 are usually implemented as closed rectangular rings that are located around the periphery of the chip. As shown in FIGS. 1A and 1B, the esdPlus and esdMinus rings 120 and 122 can be left floating (i.e. not connected to GND or VDD). However, in most ESD applications, esdPlus ring 120 is usually connected to the highest VDD voltage and esdMinus ring 122 is usually connected to ground (VSS).
In operation, ESD protection circuit 112 protects chip 100 against ESD damage by providing a low impedance current path between the two pins 114 that are being zapped. This low impedance current path ensures that the pin voltage remains within acceptable limits during a zap, protecting the chip from being damaged.
For example, as shown in FIG. 1A, if pin 114-1 is zapped positive with respect to pin 114-2, ESD protection circuit 112 allows the ESD current Izap to flow in from pin 114-1, up through diode 116-1, down through ESD switch 124, up through diode 118-2, and out to pin 114-2. Similarly, as shown in FIG. 1B, if pin 114-1 is zapped negative with respect to pin 114-2, ESD protection circuit 112 allows the ESD current Izap to flow in from pin 114-2, up through diode 116-2, down through ESD switch 124, up through diode 118-1, and out to pin 114-1.
As illustrated in FIGS. 1A and 1B, ESD switch 124 only closes during an ESD event, and must remain open during normal chip operation. Furthermore, in accordance with the above description, ESD switch 124 is only required to conduct current in one direction. Thus, independent of whether pin 114-1 is being zapped positive with respect to pin 114-2, or negative with respect to pin 114-2, the ESD current Izap flows in the same direction through ESD switch 124. In other words, ESD switch 124 is a unidirectional switch.
When a human body model (HBM) ESD test is being performed, an ESD zap voltage must be applied with an ESD Zap generator. FIG. 2 shows a schematic diagram that illustrates a prior-art ESD zap generator 200. As shown in FIG. 2, ESD zap generator 200 consists of three serially connected components: a 100 pf capacitor Czap, a 1.5K resistor Rzap, and a voltage generator Vzap.
The voltage generator provides the ESD zap voltage by ramping up from 0V to a peak zap voltage (Vzap-peak) in 6 ns. The 6 ns ramp time accounts for the inductance of the human body. For example, in a 4 KV zap test, the zap voltage would ramp up from 0V to 4 KV in 6 ns, resulting in a peak zap current of 2.7 amps (4 KV divided by 1.5K). This calculation assumes that the maximum equivalent resistance allowed between the two pins being zapped is much less than 1.5K ohms. (This is always the case, as explained in greater detail below.)
The peak ESD transient voltage allowed at a zapped I/O pin depends upon the gate oxide thickness of the CMOS transistors that are connected to the pins. Using a 0.13 micron process as an example, the nominal transistor gate oxide thickness is approximately 20 angstroms, resulting in a maximum allowable peak pin transient voltage of approximately 4V.
In the above example, the peak pin transient voltage is 4V, and the peak ESD current (for a 4 KV zap) is 2.7 amps. Thus, the maximum ‘equivalent resistance’ allowed between the two pins being zapped is only 1.48 ohms (4V divided by 2.7 A). As previously stated, this equivalent resistance is much less than the 1.5K Rzap value.
Referring again to FIGS. 1A and 1B, the maximum equivalent resistance allowed between two zapped I/O pins 114 is the total resistance of the following ESD components connected in series: two forward biased ESD diodes, one ESD switch, and the metal resistance of the esdPlus/esdMinus rings that connect these components together. In the above example, the total resistance of all components in the ESD current path is only 1.48 ohms. In other words, each component in the ESD current path must have extremely low resistance.
FIG. 3 shows a schematic diagram that illustrates a prior-art ESD protected chip 300. Chip 300 is similar to chip 100 and, as a result, utilizes the same reference numerals to designate the structures which are common to both chips. As shown in FIG. 3, chip 300 differs from chip 100 in that chip 300 has an ESD switch 124 placed in each corner of chip 300.
As discussed above, the ESD switches 124 shown in FIGS. 1A-1B and FIG. 3 must close only during an ESD event (i.e. they must remain open during normal chip operation). In addition, the ESD switches 124 must also remain open while the chip is being powered up (i.e. while the VDD voltage is rising from 0V to its final DC value). If all of these conditions are not met, catastrophic events can occur.
For example, if the ESD switches 124 were to close during normal chip operation (or while chip 300 is being powered up), DC paths would exist from any pin 114 to all of the other pins 114 (through the upper/lower ESD diodes 116/118, the ESD switch(s) 124 and the esdPlus/esdMinus rings 120 and 122). Of course, this condition would cause the chip to malfunction.
Furthermore, assuming that esdPlus ring 120 is tied to the power supply voltage VDD and esdMinus ring 122 is tied to the ground line VSS (which is usually the case), if the ESD switches 124 were to close while chip 300 is being powered up, the VDD power supply would be effectively shorted to VSS until the ESD switches 124 opened (i.e. no ESD diodes would be involved).
ESD events usually last for only a short period of time, on the order of 10 ns to 100 ns. Furthermore, assuming that the VDD power supply is being derived from the 60 Hz AC line, the VDD voltage cannot rise faster than 4 ms (¼ cycle of the 60 Hz AC line frequency). In addition, in battery powered applications, the VDD rise time usually cannot rise faster than a microsecond or so. Thus, because an ESD event is much faster than a VDD power-on event, these two events can be easily distinguished from one another. From a circuit perspective, this can by accomplished by employing an ESD switch with a simple RC time constant.
FIG. 4 shows a schematic diagram that illustrates a prior-art ESD switch 400 that is based upon an RC time constant. ESD switch 400 can be used to implement one ESD switch 124. Referring to FIG. 4, ESD switch 400, which is sometimes known as a ‘triggerswitch,’ has five components: three transistors P1, N1, and N2, one resistor R1, and one capacitor C1. Three of the components define a transistor circuit 408 that includes transistors P1 and N1, which form a P1/N1 inverter 410, and NMOS transistor N2. The remaining two components (resistor R1 and capacitor C1) define an RC time constant circuit 412.
The switch portion of triggerswitch 400 is provided by NMOS transistor N2. Thus, when transistor N2 is turned on during an ESD event, transistor N2 essentially acts as a closed switch, ‘shorting’ esdPlus ring 120 to esdMinus ring 122.
The trigger portion of triggerswitch 400 is provided by P1/N1 inverter 410, and resistor R1 and capacitor C1 of RC time constant circuit 412. RC time constant circuit 412 defines how quickly the input voltage to P1/N1 inverter 410 can follow the rising voltage on the esdPlus ring 120. As shown in FIG. 4, the supply voltage for P1/N1 inverter 410 comes from the esdPlus ring 120. Furthermore, the input voltage to P1/N1 inverter 410 can turn transistor switch N2 on or off.
Since the risetime of the VDD power supply is much slower than the risetime of an ESD event, the R1*C1 time constant can be chosen such that it is much shorter than the risetime of the VDD power supply, but much longer than the risetime of an ESD event. As a consequence of this, and as described in greater detail below, triggerswitch 400 in FIG. 4 will remain off while VDD is rising, but it will turn on during an ESD event.
Referring to FIG. 4, and as described above, in most ESD applications esdPlus ring 120 is normally connected to VDD and esdMinus ring 122 is normally connected to VSS. Thus, as the VDD power supply voltage begins to rise during a normal power-on sequence, the voltage on esdPlus ring 120 will begin to rise. Moreover, as the voltage on esdPlus ring 120 begins to rise, the voltage at the input of P1/N1 inverter 410 will also begin to rise at a slightly slower rate, due to the R1*C1 time constant.
Consequently, while the VDD voltage is rising, the voltage at the input of P1/N1 inverter 410 will closely follow the rising VDD voltage on esdPlus ring 120. Because of this, the output of P1/N1 inverter 410 will remain close to ground while the VDD voltage is rising. As a consequence, transistor switch N2 will remain off during chip power-up, which is exactly the required circuit behavior.
As described above, the R1*C1 time constant can be made much longer than the risetime of an ESD event. As a consequence of this, and as described in greater detail below, triggerswitch 400 in FIG. 4 will turn on during an ESD event.
Prior to a power-off ESD event (power-off zap), the voltages on all of the nodes in FIG. 4 will initially be at 0 volts (ground). Therefore, capacitor C1 in FIG. 4 will be in a discharged state prior to a power-off zap.
Because the R1*C1 time constant is much longer than the time constant of an ESD event, when an ESD event occurs, the voltage on esdPlus ring 120 will rise much faster than the voltage on capacitor C1. In other words, the voltage on capacitor C1 will remain close to ground during a power-off ESD event.
As a consequence of this, the input voltage to P1/N1 inverter 410 in FIG. 4 will also remain close to ground during a power-off ESD event. Therefore, as the voltage on esdPlus ring 120 rises during a power-off ESD event, the inverter output voltage will also rise, turning on switch transistor N2 in FIG. 4. This, in turn, provides a low impedance path for the ESD zap current, from the esdPlus ring 120 to the esdMinus ring 122.
Referring to FIG. 4, when the ESD zap current begins to decrease, the voltage on esdPlus ring 120 will also begin to decrease. This, in turn, will cause the gate voltage of switch transistor N2 to decrease. This gate voltage decrease will ultimately cause switch transistor N2 to turn off, effectively ending the ESD event.
FIGS. 5A-5C show waveform diagrams that illustrate an example of a prior-art 4 KV power-off zap. FIG. 5A shows the 4 KV zap voltage V1 that is being applied between the two zapped pins, in accordance with the HBM model (human body model).
In conjunction with FIGS. 1A and 1B, FIG. 5B shows the zap voltage V2 at a pin 114 that is being positively zapped, and FIG. 5C shows the zap voltage V3 at another pin 114 that is being negatively zapped.
Referring to FIG. 5A, the ESD zap voltage V1 begins at 0 volts and rises to a 4 KV peak zap voltage ZV1. In accordance with the HBM, the risetime of the ZV1 zap voltage is equal to 6 ns, which accounts for the inductance of the human body.
Referring to FIG. 5A, by the time that the zap voltage V1 has risen to only 40V, the voltages V2 and V3 have already reached their peak voltages ZV2 and −ZV3 respectively, after which time both voltages begin to decay. In other words, after the voltages V2 and V3 have peaked, the ESD event has effectively ended, even though all of the circuit waveforms have not yet decayed to zero.
Of course, an ESD event will have ended successfully if the magnitudes of both peak pin-to-substrate voltages (ZV2 and −ZV3) are less than the maximum pin-to-substrate voltage allowed. Conversely, an ESD event will have ended unsuccessfully if the magnitude of either one of the peak pin-to-substrate voltages is greater than the maximum pin-to-substrate voltage allowed.
As described in greater detail below, ESD protection circuit 112 cannot protect CMOS chips after they have been powered up. In other words, ESD protection circuit 112 is totally unsuitable for protecting CMOS chips under power-on operating conditions, after they have been mounted onto a printed circuit board (PCB). Of course, this is a very serious limitation.
As described above, in most ESD applications, esdPlus ring 120 is connected to VDD and esdMinus ring 122 is connected to VSS (ground). Thus, after a CMOS chip has been powered-up, the voltage on esdPlus ring 120 will be equal to VDD, and the voltage on esdMinus ring 122 will be equal to 0V (ground). Because of these operating conditions, the voltage on capacitor C1 will be equal to VDD. As a consequence of this, the input of P1/N1 inverter 410 in FIG. 4 will also be equal to VDD, and the inverter output voltage will be equal to 0V (ground). Moreover, because the output of inverter 410 is 0V, switch transistor N2 will be held in its turned-off state under powered-up operating conditions.
Thus, if an ESD zap occurs while a chip is powered-up, an ESD zap current will begin to flow. As the ESD zap current increases, it will cause the voltage on esdPlus ring 120 to increase. Furthermore, because the R1*C1 time constant in FIG. 4 is much greater than the risetime of an ESD event, the voltage on capacitor C1 in FIG. 4 will remain close to VDD during the entire ESD zap. Consequently, the input to P1/N1 inverter 410 will also remain close to VDD during the entire ESD zap. Because of this, the output of P1/N1 inverter 410 will be forced to remain close to 0V (ground) during the entire ESD zap.
Moreover, because the output of P1/N1 inverter 410 remains close to 0V, switch transistor N2 will be forced to remain in its turned-off state, during the entire powered-up ESD zap. Consequently, because switch transistor N2 remains off, the ESD zap current will not be able to flow from a positively zapped pin to a negatively zapped pin. In other words, the zap current will not be able to flow from esdPlus ring 120 to esdMinus ring 122. Of course, this circuit condition causes the voltage at a positively zapped pin to increase until it exceeds the maximum gate-to-substrate voltage allowed. As a consequence of this, one or more of the transistors connected to a positively zapped pin will be destroyed by a power-on ESD zap.
FIG. 6 shows a schematic diagram that illustrates a prior-art ESD protected chip 600. Chip 600 is similar to chip 300 and, as a result, utilizes the same reference numerals to designate structures that are common to both chips.
As shown in FIGS. 3 and 6, chip 300 and chip 600 both contain I/O cells 110, each of which includes an upper ESD diode 116 and a lower ESD diode 118. Furthermore, chip 300 and chip 600 also contain a high current esdPlus ring 120 and a high current esdMinus ring 122.
Nevertheless, chip 600 differs from chip 300 in that chip 600 utilizes an ESD switch 608 in lieu of the ESD corner switches 124 that are utilized by chip 300. ESD switch 608 is similar to ESD switch 400 and, as a result, utilizes the same reference numerals to designate structures that are common to both switches.
Referring to FIG. 6, it can be seen that ESD switch 608 is identical to switch 400, except that ESD switch 608 has a transistor circuit 408 located in each I/O cell 110, and an RC time constant circuit 412 located in each corner of chip 600.
As further shown in FIG. 6, chip 600 also differs from chip 300 in that chip 600 includes an esdTiming ring 610. EsdTiming ring 610 connects the four RC time constant circuits 412 located in the four corners of chip 600 to the inputs of the distributed P1/N1 inverters 410 of the transistor circuits 408 located inside of each I/O cell 110.
In addition, because esdTiming ring 610 only carries low current (i.e. the ESD timing signal), the metal width of esdTiming ring 610 can be made very small. In other words, the resistance of esdTiming ring 610 can be relatively high because the voltage on esdTiming ring 610 is not required to change during a power-off ESD zap (i.e. the ring voltage must remain close to 0V).
Chip 600 is known as a ‘distributed slave clamp’ circuit because the high current switch (clamp) transistors N2 are now distributed inside of each I/O cell 110, instead of being located in the four corners of chip 600. Thus, when a power-off ESD event occurs, all of the switch transistors N2, in all of the I/O cells 110 will turn on, providing very low resistance connections (in parallel) from esdPlus ring 120 to esdMinus ring 122.
Although it is ‘traditional’ to employ four timing resistors R1, and four timing capacitors C1, in the four corners of chip 600, the four timing resistors R1 are in parallel with each other. Similarly, the four timing capacitors C1 are also in parallel with each other. Thus, for power-off ESD zaps, it is permissible to connect only one R1 element, and only one C1 element, to esdTiming ring 610.
Although the circuit topology of chip 600 is somewhat different from the circuit topology of chip 300, both chips operate in exactly the same manner. In other words, both chips suffer from the severe limitation that they cannot protect against ESD zaps that occur during normal power-on chip operation, with VDD voltage already applied to the chip. Because of this limitation, there is a great need for an improved ESD protection circuit that can protect against power-on zaps, and can also protect against power-off zaps.